The present invention relates to an electronic device including a shielded electronic element and a method for manufacturing a shielding structure.
As a result of research in technology for miniaturizing elements, microelectromechanical system (MEMS) devices have been developed. Such an electronic device is formed on a semiconductor wafer and packaged. Examples of such a package include a can package, which uses a metal cap for sealing, and a ceramic package, which uses a ceramic cap for sealing.
Further, chip size package (CSP) technology has been developed for semiconductor integrated circuits laid out in high densities. A CSP is a package having a size that is about the same as a bare chip (semiconductor chip) on which a semiconductor integrated circuit is formed.
An acceleration sensor uses a package structure such as that shown in FIG. 5. In this structure, a sensor 70 is arranged on a substrate 50. Metal wiring (not shown) is connected to the sensor 70. A cap 30 seals the sensor 70. An adhesive 80 secures the cap 30 to the substrate 50.
To reduce stress between the cap 30 and the substrate 50, the cap 30 is formed from silicon, which is also used to form the substrate 50. A metal cap layer 40 is arranged on the cap 30. A bonding wire connects the metal cap layer 40 to a metal pad layer 41. The connection of the metal cap layer 40 and the metal pad layer 41 provides shielding with the cap 30.
A method for manufacturing the cap 30 will now be discussed with reference to FIG. 6.
First, referring to FIG. 6A, a silicon substrate 400 having a silicon surface with a crystalline orientation with a [100] face is prepared. Next, oxide films 410 and 420 are formed on the surfaces of the silicon substrate 400. As shown in FIG. 6B, part of the oxide film 420 is removed from one of the surfaces of the silicon substrate 400 to form a window region 425.
Next, anisotropic etching is performed. An anisotropic etching solution is used to process the silicon material. In this embodiment, tetramethyl -ammonium-hydroxide (TMAH) is used for etching. In a silicon crystal, a [111] face is only slightly etched by TMAH but the [100] face is etched at a rate of approximately 9000 μm/min. The etching rate of an oxide film is low, so an etching selectivity of approximately 5000 may be obtained in relation with a [100] face. Accordingly, an oxide film may be used as an etching stopper.
In this case, a hole 305 is formed as shown in FIG. 6C. A [111] face is formed on a side surface of the hole 305, and a [100] face is formed on a bottom surface. Etching stops when the oxide film 410 on the lower surface of the substrate 400 is reached.
Next, oxide film etching is performed to obtain the structure shown in FIG. 6D. In this case, the oxide films 410 and 420 are etched.
Subsequently, a predetermined process is performed in this state to manufacture the cap 30.
A method for manufacturing a semiconductor device that reduces the size of the device package and simplifies fabrication to reduce costs has been discussed (for example, refer to Japanese Laid-Open Patent Publication No. 2005-19966, page 1 and FIG. 3). In the technology described in this publication, a sealed device is formed on the surface of a semiconductor chip. A further semiconductor chip is attached to the surface of the semiconductor chip to seal the sealed device in a cavity formed between the semiconductor chips.
A method for manufacturing a semiconductor device that has a silicon on insulator (SOI) substrate, in which a semiconductor layer is superimposed on a semiconductor substrate with an insulation layer arranged in between, has been discussed (for example, refer to Japanese Laid-Open Patent Publication No. 2004-186228, page 1 and FIG. 1). In the technology described in this publication, an interlayer insulation layer is formed above the semiconductor layer of the SOI substrate. A mask pattern, which is used for the formation of a plurality of contact holes, is formed above the interlayer insulation layer. Then, first isotropic etching is performed to etch the interlayer insulation layer using the mask pattern as a mask. Next, anisotropic etching is performed to etch the interlayer insulation layer using the mask pattern as a mask. Subsequently, second isotropic etching is performed to etch the interlayer insulation layer using the mask pattern as a mask.
However, in the conventional cap structure described above, the metal cap layer and bonding wire are arranged on an upper surface of the cap, which increases the element height T0 (See FIG. 5). Increasing the height of the package is contrary to the goal of miniaturization. Further, for the miniaturization of MEMS devices, micro-processing is necessary. It is preferable that such processing be as simple as possible.